1. Field of the Invention
The present invention relates to a logic-in-memory circuit using magnetoresistive element, i.e., variable resistive element capable of storing information.
2. Description of the Related Art
In integrated circuits where the performance improvement of processor elements, memories, etc. is promoted with the backdrop of rapid development in fine processing technology in recent years, performance degradation due to wiring delay and increasing wiring area is becoming a serious problem. From the point of view that many of these wiring related problems arise from conventional architectures in which circuits are formed with operation functions and memory functions being separated from each other, the inventors have focused on the logic-in-memory architecture, in which systems are formed with the integration of processor elements and memories, as a method for solving the wiring related problems fundamentally, and have proposed high-performance logic-in-memory circuit technologies in which operation functions and memory functions are compactly integrated utilizing ferroelectric devices used as memory elements in ferroelectric memory (FeRAM) (refer to Non-patent documents 1 and 2).
(Logic-in-memory Circuit)
In FIGS. 1(a) and 1(b) shown is a common VLSI 10 consisting of logic circuits and memory circuits (refer to FIG. 1(a)) and a logic-in-memory VLSI 20 (refer to FIG. 1(b)).
The processing in the common VLSI 10 is carried out by reading data out of the memory circuits 11 and 12 through a bus 15, performing operations in the logic circuits 17 and 18, and writing the operation results into the memory circuits 11 and 12 through the bus 15.
In the logic-in-memory VLSI 20 wherein nonvolatile devices are used as shown in FIG. 1(b), bottleneck in data transfer on a global wiring (bus 15) can be reduced significantly by distributing memory functions among operation circuits 22 and localizing the data transfer between a processor element 24 and a memory 25. Also, the use of nonvolatile devices makes it possible to hold stored data without power supply voltage, which allows leakage current of memory elements to be reduced significantly, having potential for substantial reduction in power consumption.
The logic-in-memory technique, which enables the amount of wiring to be reduced significantly by localizing the data transfer between processor element and memory, is useful in establishing highly parallel operation systems that have no bottleneck in data transfer, and therefore it is actually possible to realize gate-level pipeline multipliers and complete parallel associative memories compactly.
These logic-in-memory circuit technologies use nonvolatile memory devices to form operation circuits, whereby the application range thereof depends highly on the characteristics of the devices. Therefore, to expand the application range of the logic-in-memory architecture, it is important to utilize the excellent characteristics of various nonvolatile memory devices as well as ferroelectric capacitors in the logic-in-memory circuit.
(TMR Element)
It is possible to utilize magnetoresistive elements, particularly, ferromagnetic tunnel magnetoresistive (TMR) elements used mainly as memory elements in ferromagnetic memory (MRAM) as a new elemental technology in logic-in-memory circuit (refer to Non-patent document 3). TMR elements, which are also called ferromagnetic tunnel junction elements (MTJ elements), can perform electrical data access to magnetic memory elements by utilizing the spin-tunnel magnetoresistive effect that changes the electrical resistance in accordance with the spin (magnetization) direction in a ferromagnetic material, which makes it possible to realize excellent memory functions of magnetic storage in integrated circuits, such as non-volatility, nondestructive read-out, high-speed access, and infinite rewritability.
The structures and operations of TMR element are shown in FIGS. 2(a), 2(b), 2(c), 3-1(a), 3-1(b) and 3-1(c). As shown in the cross sectional view of FIG. 2(a),a TMR element 30 comprises a ferromagnetic layer (free layer) 32 where the spin (magnetization) direction changes in accordance with an externally applied magnetic field, an ultrathin nonmagnetic layer 34 and another ferromagnetic layer (fixed layer) 36 having a constant spin direction independent of externally applied magnetic field, having a three-layer structure of the ferromagnetic, nonmagnetic and ferromagnetic layers. To the fixed layer 36 is applied a diamagnetic layer 38 to fix the spin direction in the ferromagnetic layer 36. FIG. 2(b) is a symbolic representation of the TMR element 30. A major characteristic of TMR element is that the electrical resistance of the element 30 increases or decreases rapidly as the spin direction in the free layer 32 is changed by an external magnetic field as shown in the hysteresis characteristics of FIG. 2(c). For example, when the spin directions in the free layer 32 and the fixed layer 36 are reversely parallel with each other, the tunnel current in the nonmagnetic layer 34 decreases, resulting in a high resistance. On the contrary, when the spin directions in the free layer 32 and the fixed layer 36 are parallel with each other, the tunnel current in the nonmagnetic layer 34 increases, resulting in a low resistance. Therefore, under a rule that the stored data is represented by “1” in the case of a parallel spin direction, while by “0” in the case of a reversely parallel one, the TMR element 30 can be considered as a nonvolatile memory element that holds stored data as resistance value.
Write operation into the TMR element 30 is performed by applying a current to a wiring adjacent to the TMR element and generating a magnetic field around the wiring. Write operations are shown in FIGS. 3-1(a), 3-1(b) and 3-1(c). As shown in FIG. 3-1(a), currents IB and IW are applied, respectively, to two adjacent wirings that run at right angles to one another (a bit line 42 and a write line 44) to perform a write operation by a synthetic magnetic field HB+HW. FIGS. 3-1(b) and 3-1(c) show that data “0” or “1” is written in accordance with the direction of the current IB. As described, data can be written selectively into a cell on a memory array according to whether or not there flows the current IW through the write line 44, and therefore this kind of write operation is widely used for MRAM.
Stored data read operations from the TMR element 30 are shown in FIGS. 3-2(a), 3-2(b) and 3-2(c). Stored data read operation is performed, as shown in FIG. 3-2(a), by applying a voltage from the bit line 42 to the TMR element 30 and detecting a current IR that flows according to the resistance value of the TMR element 30 (refer to FIGS. 3-2(b) and 3-2(c)). In this case, where the current IR on the bit line 42 is sufficiently smaller than the current IB in the write operation, no stored data is destroyed. That is, nondestructive read operation can be performed.
When realizing a memory element using a TMR element in an actual circuit, the increase of the magnetoresistance (MR) ratio ((Rmax−Rmin)/Rmin) defined by the maximum resistance Rmax and the minimum resistance Rmin in FIG. 2(c) is important for performance improvement. Currently, there are proposed TMR elements with large MR ratios of 45 to 55% (refer to Non-patent document 3).
TMR element allows electrical data access to magnetic memory elements to be electrically performed by utilizing the spin-tunnel magnetoresistive effect that changes the resistance value in accordance with the spin (magnetization) direction in a ferromagnetic material, which makes it possible to realize excellent memory functions of magnetic storage in integrated circuits, such as non-volatility, nondestructive read-out, high-speed access, and infinite rewritability.
It is noted that there is introduced a logic-in-memory circuit using TMR elements in Non-patent document 4.
A giant magnetoresistive element (GMR element) can be cited, for example, as another type of magnetoresistive element other than TMR element. A significant difference between GMR element and above-mentioned TMR element is the physical mechanism for the magnetic change of resistance values. In the case of TMR element, when applying a voltage perpendicularly to a nonmagnetic layer (tunnel layer, which includes AlO2 mainly), the resistance value is changed by the tunnel magnetoresistive effect in which tunnel current changes according to whether the magnetization directions in two ferromagnetic layers are parallel or reversely parallel to each other. Meanwhile in the case of GMR element, when applying a voltage parallel to a nonmagnetic layer (which includes Cu mainly), the degree of electron scattering in the nonmagnetic layer is changed according to whether the magnetization directions in two ferromagnetic layers are parallel or reversely parallel to each other, resulting in a change of the resistance value (refer to Non-patent document 5).
The basic operations for GMR element are similar to those for TMR element, that is, read operation is performed by detecting the resistance value, while write operation is performed by applying an external magnetic field and changing the magnetization direction in ferromagnetic layers.
[Non-patent document 1] T. Hanyu, H. Kimura, M. Kameyama, Y. Fujimori, T. Nakamura and H. Takasu, “Ferroelectric-Based Functional Pass-Gate for Fine-Grain Pipe lined VLSI Computation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC)
[Non-patent document 2] H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori, T. Nakamura and H. Takasu, “Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 160–161, February 2003.
[Non-patent document 3] M. Motoyoshi, K. Moriyama, H. Mori, C. Fukumoto, H. Itoh, H. Kano, K. Bessho and H. Narisawa, “High-performance MRAM Technology with an Improved Magnetic Tunnel Junction Material,” in IEEE Symp. on VLSI Technology Dig. Tech, Papers, pp. 212–213, June 2002.
[Non-patent document 4] H. Kimura, T. Hanyu and M. Kameyama, “Logic-in-Memory VLSI Configuration Using Nonvolatile Device,” TECHNICAL REPORT OF IEICE ICD 2003-5 (2003-04).
[Non-patent document 5] Betty Prince, “Emerging Memories-Technologies and Trends,” Kluwer Academic Publishers, 2002